Retrochallenge 2017/10 #7: Final report

At the beginning of the Retrochallenge, I had the following goals:

  • Make a Verilog implementation of the SP0256-AL2.
  • Synthesize and test the design on a Terasic DE0 FPGA board.
  • Cut corners.
  • Learn Verilog.
  • Have fun!

I think I succeeded on all five points.

The platform agnostic Verilog code for the Speech256 is available on GITHUB. I also have a Quartus II project available to run a demonstration on the Terasic DE0 board (no not Digilent, as I mentioned many times before.. derp).

I cut quite a few corners by not implementing the compressed ROM format of the SP0256-AL2, but using my own encoding and controller.

I learned Verilog in the process, although Clifford Wolf did have a few pointers on my coding style regarding non-blocking assignments…

And finally, I synthesized and tested the design on the DE0 board:

… and I had fun doing this; I hope you liked it too!

A big shout-out to John W. Linville for running the Retrochallenge 2017/10.

Until next time — Retrocompute!

Retrochallenge 2017/10 #6


The last two days, I spent several hours debugging the filter engine. The filter didn’t want to behave, meaning the output values were going all over the place.

The debugging process involved setting up the filter to the ‘EH’ allophone and going through the changing filter states, one by one, to find the differences between a known/good model, which I had made in MATLAB, and the Verilog code. Using this method, I finally tracked this down to a signed/unsigned problem in the serial/parallel multiplier.

Will it float or will it sink?

The source-filter model, controller and top-level Speech256 block were mostly complete. To test the final design, all I needed to do was feed a string of allophones to the Speech256 top-level block and capture the simulated output to the DAC.

I set up the following allophones: 0x1B, 0x07, 0x2D, 0x35, 0x03, 0x2E, 0x1E, 0x33, 0x2D, 0x15, 0x03.

This is the result:


So YES! it floats!


Next: actually get it synthesized and running on the DE0 FPGA board…

Retrochallenge 2017/10 #5

I’ve been working on the controller part of the Speech256. The current status is that is it mostly working: it sends pitch, duration, voiced/unvoiced and filter coefficients control signals to the source-filter model.


Coefficient translation

To save command ROM space, the designers of the SP0256 command ROM chose to encode the filter coefficients in a 8-bit sign-magnitude format instead of the 10-bit format needed by the filter engine. To be clear, the Speech256 project does not use a copy of the SP0256 ROM; it uses a custom format. However, the bit-depth reduction technique is used to keep the control ROM small.

The SP0256 contains an expansion circuit that translates the 8-bit format into the 10-bit format. The SP0256 seems to use the same translation table as the SP0250, which is documented in its Applications Manual:


The table pertains to the (7-bit) magnitude part of the (8-bit) sign-magnitude only: positive and negative numbers are translated by the same table, keeping the sign untouched.

Although the manual claims it uses a lookup ROM, the content looks like a piece-wise linear curve which can therefore be implemented without a ROM. I found four lines (C1 .. C4) that represent the table quite accurately:SP0256_quant_curve
The following code snippet will translate a 7-bit magnitude into a 9-bit magnitude according to the table …

if x < 38
    return x*8;
if x < 69
    return 301 + (x-38)*4;
if x < 97
    return 425 + (x-69)*2;
if x < 128
    return 481 + (x-97);

… except for x=2, where the result should be 12 instead of 16. Note that the C1 line also has a slight offset error but I think this translation function is most likely good enough.

The convenient factors-of-two scaling found, makes me suspect the function was meant to be implemented directly in logic, not in a ROM.

Time is running out, so I’d better get on implementing the above!


Retrochallenge 2017/10 #4

Another small update of the Retrochallenge 2017/10 Speech256 project. The source part is finished! It can produce both the pulse wave and noise:



Here’s the audio for the brave:

Noise generator

In case you were wondering, the linear feedback shift register used for the noise generator is a single Verilog line:

lfsr = {lfsr[15:0], lfsr[16] ^ lfsr[2]}

The updated Verilog source code is up on the Github page!


Up next will be integrating the filter engine and the source to complete the source-filter model of the synthesizer.

Retrochallenge 2017/10 #3

During the past few days I’ve managed to squeeze some time out of my schedule to make progress on the Verilog code for the Speech256 synthesizer.

Basically, I think I have the 12-pole filter working. This is the most complicated part of the project, with three shift registers holding the filter coefficients and the filter states:


The coefficient shift register is used as a roundabout, which avoids the use of an actual addressable structure, like a RAM. It also simplifies loading a new set of coefficients into the filter engine, as these can simply be served in a serial fashion, reducing the interface complexity to the Speech256 controller.

The multiplier shown is implemented using a shift-and-add technique, which has a reduced speed but a lower resource requirement compared to a fully parallel implementation.

The 12-pole filter control logic (not shown) was a bit tricky due to the serial nature of many of the components, see the meaningless screenshot here:


The most recent code is up on my Speech256 Github page..

Retrochallenge 2017/10 #2

Here is the first real RC2017 update in the form of a video on the inner workings of the SP0256-AL2 speech synthesis chip.

It took a lot longer to produce than I originally thought, partly because I had a severe cold and sounded like a wet newspaper, and partly because open-source video recording and editing is still a P.I.T.A, apparently.

Noise shaper system equations

Here are a few quick notes on digital noise shapers, primarily for my own reference.


Here we have a traditional noise shaper setup, consisting of an Nth-order loop filter and a quantizer:


When a linear model is assumed, the noise transfer function (NTF) H_{ntf} can be expresses as a function of the loop filter:

H_{ntf}(z) = \frac{1}{1+H_{loop}(z)}.

The loop filter also changes the frequency response of the input signal:

H_{sig}(z) = \frac{H_{loop}(z)}{1+H_{loop}(z)}.

Assuming the loop gain is very high in the lower part of the spectrum, where the desired signal is present, this frequency response can be approximated as:

H_{sig}(z) = \frac{H_{loop}(z)}{1+H_{loop}(z)} \approx \frac{H_{loop}(z)}{H_{loop}(z)} = 1.

In effect, given enough in-band loop gain, the frequency domain distortion is negligible.

Causal loop filters

Given a desired noise transfer function H_{ntf}, the loop filter can be derived as follows:

H_{loop}(z) = \frac{1}{H_{ntf}(z)} - 1

Now, splitting the NTF into its poles A(z) and zeroes B(z), the loop filter can be expressed as:

H_{loop}(z) = \frac{A_{ntf}(z)}{B_{ntf}(z)} - 1

and therefore:

H_{loop}(z) = \frac{A_{ntf}(z) - B_{ntf}(z)}{B_{ntf}(z)}.

For the loop to be causal, the loop filter must have at least one pure delay. Given that A(z) = 1 - a_1 \cdot z^{-1} - a_2 \cdot z^{-2} - \ldots - a_n \cdot z^{-n}, if we force the first coefficient of B(z), i.e. b_0, to be equal to 1, the first coefficient of the resulting loop filter numerator will be zero and the loop filter is guaranteed to have at least one delay.