The last two days, I spent several hours debugging the filter engine. The filter didn’t want to behave, meaning the output values were going all over the place.
The debugging process involved setting up the filter to the ‘EH’ allophone and going through the changing filter states, one by one, to find the differences between a known/good model, which I had made in MATLAB, and the Verilog code. Using this method, I finally tracked this down to a signed/unsigned problem in the serial/parallel multiplier.
Will it float or will it sink?
The source-filter model, controller and top-level Speech256 block were mostly complete. To test the final design, all I needed to do was feed a string of allophones to the Speech256 top-level block and capture the simulated output to the DAC.
I set up the following allophones: 0x1B, 0x07, 0x2D, 0x35, 0x03, 0x2E, 0x1E, 0x33, 0x2D, 0x15, 0x03.
This is the result:
So YES! it floats!
Next: actually get it synthesized and running on the DE0 FPGA board…