Retro Challenge #3

The HD6309 computer’s schematic is getting to a stage where I can share it. Beware, it most likely will contain errors!HD6309P_Schematic_8_4_2017

Here is a PDF version: HD6309 Computer schematic.

Schematic walkthough

At the top left is the HD6309 processor. I have kept the interface complexity to a minimum. The memory interfaces are fast enough to do away with wait-states, so the MRDY is tied to VCC as are the IRQ and NMI interrupt signals. Only the fast interrupt signal is currently used (by the UART). In this design, DMA support is not used, so BS and BA are ignored, and DMA/BREQ is tied high. The CPU halting capability, useful for single-stepping the CPU, is also not used and tied high to VCC.

The top level address decoding is handled by U4, an ATF16V8B programmable logic chip (GAL). I have a few of these and they should program fine with my TL866 programming. Note: the ATF16V8C does not!

The decoder emits chip select signals for the RAM, ROM and IO spaces. In addition, it creates separate READ and WRITE signals from the CPU’s R/W and E signal. The documentation mentions the need for gating R/W with E to avoid writing incorrect values into the RAM or peripherals. This is done inside the GAL.

The GAL also generates the signals (RAM_MAP and RAM_FIX) for the memory mapper. The top address bits (A15..A19) of the 1MB static RAM are set to the all-zero word by the 74HC(T)541 line driver (U8) or to a programmable word by the 74HC(T)574 register (U7). The contents of register U7 can be set by the CPU.

The IO space is decoded by a second ATF16V8B GAL (U2). It generates the chip selects for the SC16C550B UART (U11) and the buffered expansion port (P3 and P4). Note the different number of pins on the two connectors. This was done so that a user would have no problems knowing which way ’round to plug in an expansion board.

The interrupt line of the UART is connected to /INT of the CPU through a transistor. The transistor provides the needed inversion and it’s also an open collector output so other devices can pull /INT low, should this be needed in the future.

An 8K EEPROM (U12) is connected to the CPU. Only the top 4K of this memory is mapped into the address space of the CPU, at $F000.

Will it float or will it sink?

Using programmable logic for address decoding and other essential parts of the circuit de-risks the design to a large extent. Murphy, of course, dictates that the flexibility will be in the wrong part of the circuit 🙂

The next step is to layout a PCB for the computer. I hope I can get the design out the door in time to build a working computer before the end of April!

Next time: layout of the PCB!


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