Retro Challenge #1

Today is April 1st; the start of the Retro Challenge 2017/04! (no joke).

During this Retro Challenge period, I am going to design and hopefully build a working computer around the HD6309 8-bit CPU.

I had ordered HD63C09P and HD63C09EP devices from different sellers on eBay. Some of the HD6309 CPUs showed up on my doorstep yesterday! Perfect timing!

HD6309P

Details of the HD63C09P

The Hitachi HD6309 is a powerful 8-bit microprocessor that is an enhanced version of the well-known Motorola MC6809. The processor is pin compatible with the MC6809. Although there are some subtle differences, systems designed for the MC6809 will most likely also run with an HD6309.

63C09P_pinout

HD6309P pinout

There are two versions of the HD6309; one with a built-in crystal oscillator/clock generator and one without. The latter version has the letter ‘E’ in the suffix of the part name, which probably means ‘External’. While the ‘E’ version is more flexible, it is also harder to use because it requires an externally generated quadrature clock and DMA handling logic — buyer beware!

The version I have is the HD63C09P, with the ‘C’ indicating that it will run at an internal clock rate of 3 MHz. The internal clock is generated from a 4x higher external clock or crystal connected to the XTAL and EXTAL pins.

The address space is 64K and all peripherals are memory mapped. Slow memory or peripherals can be accomodated by stretching the clock using the MRDY pin. The datasheet states that the maximum stretch duration is 5 microseconds. While this may be correct for the MC6809, I doubt this is true for a fully-static CMOS design like the HD6309.

What goes where in memory is mostly up to the system designer, except for the HD6309 interrupt vector table. This is fixed at the top of the memory map:6309_vectors

Two signals, BA and BS, tell the user about the state of the processor:6309_state

These signals are used by external DMA logic to figure out when the bus is available for use by another bus master.

Internal structure

The internal structure of the HD6309 is shown by the figure below:

hd6309_internals.png

Note that this figure, taken from the official datasheet, does not show the extended features of the HD6309. It seems these features were never officially documented by Hitachi.

The programming model, showing the registers, is shown in the following figure:

HD6309_programming_model

Again, this is a copy from the official documentation. The HD6309 contains several additional registers not shown.

The 6309 has a two 8-bit accumulators (A and B) for computational use. These accumulators can by combined to form a 16-bit accumulator ‘D’. In addition, two 16-bit index registers, X and Y, are available for easy memory access. The CPU also has two stack pointers, S and U.

Extensions

The HD6309 has more registers and instructions than a MC6809. Here is a brief overview of them:

  • Two additional 8-bit registers: E and F.
  • An additional 16-bit register W formed by combining E and F.
  • A 32-bit register Q formed by combining D and W.
  • 16×16 multiplication instruction.
  • 32/16 bit and 16/8 bit hardware division instructions.
  • Interruptable memory-to-memory block moves.
  • Inter-register arithmetic and logical operations.
  • Byte manipulation instructions.
  • Single-bit operations.
  • Several new indexed addressing modes.
  • Illegal opcode trap interrupt.
  • Division-by-zero trap interrupt.
  • 16-bit arithmetic instructions.

When the 6309 starts or is reset, the CPU is in emulation mode; it behaves mostly as a 6809. Through a set of special instructions, the 6309 can be switched into native mode. In native mode, a few additional features become available and many instructions execute in fewer clock cycles.

You can find more information about all the different enhancements in ‘ The 6309 Book: Inside the 6309‘ by Chris Burke.

Related literature

Next..

This post was a general overview of the hardware and software capabilities of the HD6309 processor, mainly to get myself acquainted with the HD6309. The next steps are to figure out which peripherals are needed and what the memory map of the computer will look like.

 

 

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